Semiconductor memory device with test mode

ABSTRACT

In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the testing method carries out resetting the address of the defective region stored in the first register and the trimming value stored in the second register, and setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-303854, filed Oct.3, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device having apulse generator circuit and an internal voltage generator circuit, thesemiconductor device being capable of adjusting values of a pulse widthof the pulse generated by these circuits and a value of an internalvoltage. More particularly, the present invention relates to anonvolatile semiconductor memory that internally generates a referencevoltage, a writing voltage, a erasure voltage, and a readout voltage.

[0004] 2. Description of the Related Art

[0005] An NAND type flash memory that is one type of nonvolatilesemiconductor memory is announced by literature such as K. Imamiya et.al. “A 130-mm² 256-Mb NAND Flash with Shallow Trench IsolationTechnology”, IEEE J. Solid State Circuits, Vol. 34, pp. 1536-1543.November 1999” or the like.

[0006] In such a nonvolatile semiconductor memory, voltage trimming anddefective cell redundancy replacement are carried out in a wafer testprocess.

[0007]FIG. 35 is a flowchart showing an outline of a conventional wafertesting process. The operating contents of each process are as follows.

[0008] In a DC test, DC checks such as contact check and standby currentare made. In Vref (reference voltage) trimming, Wref of each chip on awafer is monitored, and then, it is computed as to what a trimming valueshould be determined inn order to correct these to a target value.

[0009] Next, Vpgm (writing voltage) initial value trimming is carriedout. In a NAND type flash memory, there is employed Incremental StepPulse Programming Scheme that increments a writing voltage Vpgm from aninitial value in a stepwise manner. This method is described in “K. D.Suh et. al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step PulseProgramming Scheme”, “ISSCC Digest of Technical Papers, pp. 128-129,February 1995”, for example. In this writing method, it is required tooptimize an initial value of Vpgm in order to ensure that a write time(or write loop count) is included within a predetermined time (count).For that purpose, it is required to find a block (good block) that canbe written and erased from the inside of a memory cell array. This isbecause redundancy replacement of a defective cell is not carried out atthis step.

[0010] If a good block is found, writing is carried in that block whilean initial value of Vpgm is changed, and an optimal value is determined.

[0011] Subsequently, voltage trimming fuse cutting is carried out. Atthis step, a wafer is moved to a laser blow unit, and fuse cutting iscarried out according to the above Vref trimming and a trimming valuedetermined by Vpgm initial value trimming.

[0012] Subsequently, defective column/row detection is carried out.Here, for redundancy replacement, some data patterns are written into amemory cell array, and a defective column/row is detected.

[0013] Next, redundancy fuse cutting is carried out. Here, a wafer ismoved to a laser flow unit again, and fuse cutting of redundancyreplacement is carried out.

[0014] In this flowchart, voltage trimming fuse cutting is carried outbefore detecting a defective column/row because there is a possibilitythat, if defective column/row detection is carried out in a state inwhich an internally generated voltage such as Vpgm is shafted, a defectcannot be found.

[0015] A testing time at the above described wafer testing step isreflected in chip cost. Therefore, in order to reduce a chip cost, it isrequired to reduce a test time to the minimum while required wafertesting is carried out.

[0016] At the above described wafer test step, there are two factorsthat a test time is increased. One lies in the existence of a fuse cutstep itself. In order to carry out fuse cutting by means of laserblowing, it is required to remove a wafer from a tester, and move thewafer to a laser blow unit. Here, a time overhead is produced. At theabove described wafer test step, in particular, it is required to carryout fuse cutting separately twice, thus making the overhead moresignificant.

[0017] The second factor lies in a tester computation time, in order toreduce a test time, commands are assigned to about 100 chips at the sametime at the wafer test step, and a tester is used such that an outputcan be measured at the same time. However, such a tester cannot carryout completely in parallel an operation for computing a trimming valuefrom a monitored voltage or an operation for detecting a defectivecolumn row from a readout data pattern. A maximum of 10 chips can beprocessed in parallel. Therefore, even if data for 100 chips can beacquired at the same time, operational processing for such data must becarried out by being divided by 10 times, and here, a time overheadoccurs.

[0018] A method for reducing a time for the fuse cutting step of theabove two factors is described by the invention relating to applicationof Japanese Patent Application Publication No. 11-351396 made by theApplicant. The outline is given below.

[0019] In a nonvolatile semiconductor memory, a memory cell can storeinformation in a nonvolatile manner. Thus, if a voltage trimming valueor redundancy information is stored in a memory cell array, fuse andfuse cutting step can be eliminated. When a nonvolatile semiconductormemory is placed in a normal operation state, although it is required tostore the previous trimming value or redundancy information in apredetermined register, the storage operation, i.e., an operation foracquiring information from the inside of a memory cell array, therebystoring the information in a register may be carried out at a time whena power is supplied to a nonvolatile semiconductor memory.

BRIEF SUMMARY OF THE INVENTION

[0020] According to an aspect of the present invention, there isprovided a semiconductor device comprising:

[0021] a bit line;

[0022] a plurality of memory cells connected to the bit line; and

[0023] a sense amplifier connected to one end of the bit line; and

[0024] a defect detector circuit configured to read out data by thesense amplifier while setting a plurality of memory cells connected tothe bit line all to a non-selected state, and the other end of the bitline being connected to a predetermined potential via a switch, and anopen-circuit defect of the bit line being detected according to areadout data by the sense amplifier.

[0025] According to another aspect of the present invention, there isprovided a semiconductor device comprising:

[0026] a memory cell array in which programmable and erasablenonvolatile memory cells are arranged in column and row directions of amatrix;

[0027] an address register that can store an address of a unit of memorycells which are programmed and erased simultaneously in the memory cellarray; and

[0028] a control circuit that carries out an erase verify operationconfigured to output a “pass” or “fail” signal according to whether ornot all the memory cells targeted for erasing are erased, a write verifyoperation configured to output the “pass” or “fail” signal according towhether or not all the memory cells targeted for writing are written,and an operation activated upon receipt of a first command, for, wheneither of results of the erase verify and write verify operations is“fail”, changing data of the address register, and when the results are“pass”, disabling change of data of the address register.

[0029] According to a further aspect of the present invention, there isprovided a semiconductor device comprising a register activated by acommand input, the register having plural types of test operationsconfigured to output a “pass” or “fail” signal, wherein, if a result ofan immediately preceding test that has been carried out of the testoperations is “pass”, no data is changed, and if the result is “fail”,data is set in a predetermined signal state.

[0030] According to a further aspect of the present invention, there isprovided a semiconductor device having erase verify and write verifyfunctions comprising:

[0031] memory cells;

[0032] an address register that can store an address of a unit of memorycells which are programmed and erased simultaneously in the memory cellarray;

[0033] a first register that stores a “pass” and “fail” result after anerase verify operation;

[0034] a second register that stores a “pass” and “fail” result after awrite verify operation;

[0035] a third register provided for each erase unit, the third registerconfigured to store a first or second signal state according to whetheror not the memory cells in the erase unit are write-erasable or not; and

[0036] a control circuit activated upon receipt of a first commandinput, the control circuit making an operation such that, when at leastone of the first register data and second register data is “fail”, athird register corresponding to an address selected by the addressregister is set to a first signal state, and when both of the firstregister data and second register data are “pass”, the third register isset to a second signal state.

[0037] According to a further aspect of the present invention, there isprovided a semiconductor device comprising:

[0038] an internal circuit whose operation or function changes based ondata stored in a register; and

[0039] a control circuit that repeatedly makes a first operation tocarry out a self-judgment test for the internal circuit such that aresult of either of “pass and “fail” is outputted and a second operationto carry out a different control for the register according to the“pass” or “fail” result in the self-judgment test, wherein datareflecting the characteristics of each semiconductor device is set tothe register.

[0040] According to a further aspect of the present invention, there isprovided a semiconductor device comprising:

[0041] an internal circuit in which an output is trimmed in 2^(N)different schemes by a register capable of holding N-bit data (where Ndenotes a positive integer); and

[0042] a data setting circuit that judges in a first test the output ofthe internal circuit while the N-bit data is placed in a first state, todetermine most significant bit data of the N-bit data; judges, in a kthtest (k=2, 3, . . . N), while data from the most significant bit to a(k−1)th bit is maintained to a value determined in a first to (k−1)thtest, the output of the internal circuit with the remaining bit beingplaced in a predetermined value to determine a kth bit data; and setsdata reflecting characteristics of each semiconductor device to theregister by the N tests.

[0043] According to a further aspect of the present invention, there isprovided a semiconductor device comprising:

[0044] a memory cell array having a column region and a row region inwhich memory cells are arranged in column and row directions of amatrix;

[0045] a redundancy column region having M redundancy columns forreplacement with a defective column in the memory cell array;

[0046] M registers configured to store column addresses to be replacedwith the redundancy columns, each of the M registers including a latchplaced to a first or second signal state according to whether or not acorresponding redundancy column can be used;

[0047] a sense amplifier;

[0048] a counter that selects the M registers sequentially;

[0049] a judgment circuit that makes a judgment on whether or not dataof a selected column outputted from the sense amplifier coincides with apredetermined expected value and outputs a “pass” or “fail” signalaccording to a result of the judgment; and

[0050] a control circuit that sets a column address and the counter to astart address, when a defective column in the memory cell array is to bedetected; makes, if an output of the judgment circuit is “pass”, anincrement of the column address, and, if the output of the judgmentcircuit is “fail”, and the latch of the register selected by the counteris placed in the first signal state, stores the column address in theregister and thereafter making an increment of the column address andthe counter; makes an increment of the counter until the counter hasreached a register whose latch is placed in the first signal state, ifthe output of the judgment circuit is “fail” and the latch of theregister selected by the counter is placed in the second signal state,thereafter, stores the column address in the register, and thereafter,makes an increment of the column address and the counter, and performsthe operations until the counter has reached an end column address.

[0051] According to a further aspect of the present invention, there isprovided a semiconductor device comprising:

[0052] a memory cell array in which programmable and erasablenonvolatile memory cells are arranged in column and row directions of amatrix;

[0053] a sense amplifier;

[0054] a bit line extending in the column direction, configured totransmit data of the memory cell array to the sense amplifier; and

[0055] a column defect detecting circuit that detects a defective columnof the memory cell array, without carrying out writing and erasingoperation for the memory cells.

[0056] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device, the semiconductordevice comprising: a memory cell array in which programmable anderasable nonvolatile memory cells are arranged in column and rowdirections of a matrix; an address register that can store an address ofa unit of memory cells which are programmed and erased simultaneously inthe memory cell array; and a control circuit that carries out an eraseverify operation for outputting a “pass” or “fail” signal according towhether or not all the memory cells targeted for erasing are erased, awrite verify operation for outputting the “pass” or “fail” signalaccording to whether or not all the memory cells targeted for writingare written, and an operation activated upon receipt of a first command,for, when either of results of the erase verify and write verifyoperations is “fail”, changing data of the address register, and whenthe results are “pass”, disabling change of data of the addressregister, wherein in the method of testing a semiconductor device,series of operations comprising an erasing operation, an erase verifyoperation, a writing operation, a write verify operation and the firstcommand input are repeated a plurality of times, to find awrite-erasable region in a memory cell array.

[0057] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device, the semiconductordevice comprising a register activated by a command input, the registerhaving plural types of test operations for outputting a “pass” or“fail”, signal, wherein, if a result of an immediately preceding testthat has been carried out of the test operations is “pass”, no data ischanged, and if the result is “fail”, data is set in a predeterminedsignal state, wherein in the method of testing a semiconductor device,plural types of the test operations are carried out, and thereafter, itis judged whether or not the register data is set to a predeterminedsignal state to judge whether the semiconductor device is normal ordefective.

[0058] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device integrated on asemiconductor chip, the semiconductor device comprising a memory cellarray that comprises nonvolatile memory cells; a first register thatstores an address of a defective region in the memory cell array; aplurality of internal voltage generator circuits; and a second registerprovided corresponding to each of the plurality of internal voltagegenerator circuits, the second register storing a trimming value forsetting an internal voltage value generated by each of the internalvoltage generator circuits, the semiconductor device being integrated ona semiconductor chip, the method of testing a semiconductor device,comprising:

[0059] resetting the address of the defective region stored in the firstregister and the trimming value stored in the second register; and

[0060] setting the address of the defective region stored in the firstregister and the trimming value stored in the second register to a valueaccording to a property of each of the semiconductor chips, wherein thetesting is carried out without turning a power supply off after thepower supply has been turned on.

[0061] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device integrated on asemiconductor chip, the semiconductor device comprising an internalcircuit in which an operation or function is changed based on datastored in a register, the method of testing a semiconductor device,comprises:

[0062] a first operation configured to cause the internal circuit tocarry out a self-judgment test such that a result indicating either“pass” or “fail”, is outputted, and

[0063] a second operation configured to carry out for the register acontrol that is different depending on the result of “pass” or “fail” inthe self-judgment test, wherein the first operation and second operationare repeated alternately in a predetermined number of times to set forthe register data reflecting characteristics of each of thesemiconductor chips.

[0064] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device, the semiconductordevice having an internal circuit in which an output is trimmed in 2^(N)different schemes by a register capable of holding N-bit data (where Ndenotes a positive integer), the method of testing a semiconductordevice comprising:

[0065] judging in a first test the output of the internal circuit whilethe N-bit data is placed in a first state, to determine most significantbit data of the N-bit data;

[0066] judging, in a kth test (k=2, 3, . . . N), while data from themost significant bit to a (k−1)th bit is maintained to a valuedetermined in a first to (k−1)th test, the output of the internalcircuit with the remaining bit being placed in a predetermined value todetermine a kth bit data; and

[0067] setting data reflecting characteristics of each semiconductordevice to the register by the N tests.

[0068] According to a further aspect of the present invention, there isprovided a method of testing a semiconductor device, the semiconductordevice comprising a memory cell array in which programmable and erasablenonvolatile memory cells are arranged in column and row directions of amatrix; a sense amplifier; and a bit line extending in the columndirection, configured to transmit data of the memory cell array to thesense amplifier, wherein,

[0069] the method of testing a semiconductor device, comprisesdetermining whether or not an open-circuit, short-circuit or leak ispresented in the bit line and sense amplifier to detect a defectivecolumn of the memory cell array, without carrying out writing anderasing operation for the memory cells.

[0070] According to a further aspect of the present invention, there isprovided a method of detecting and replacing a defective column in asemiconductor device, the semiconductor device comprising a memory cellarray having a column region and a row region in which memory cells arearranged in column and row directions of a matrix; a redundancy columnregion having M redundancy columns for replacement with a defectivecolumn in the memory cell array; M registers configured to store columnaddresses to be replaced with the redundancy columns, each of the Mregisters including a latch placed to a first or second signal stateaccording to whether or not a corresponding redundancy column can beused; a sense amplifier; a counter that selects the M registerssequentially; and a judgment circuit that makes a judgment on whether ornot data of a selected column outputted from the sense amplifiercoincides with a predetermined expected value and outputs a “pass” or“fail” signal according to a result of the judgment, wherein,

[0071] the method of detecting and replacing a defective column in asemiconductor device comprising:

[0072] setting a column address and the counter to a starting address,when a defective column in the memory cell array is to be detected;

[0073] making, if an output of the judgment circuit is “pass”, anincrement of the column address, and, if the output of the judgmentcircuit is “fail” and the latch of the register selected by the counteris placed in the first signal state, storing the column address in theregister and thereafter making an increment of the column address andthe counter after;

[0074] making an increment of the counter until the counter has reacheda register whose latch is placed in the first signal state, if theoutput of the judgment circuit is “fail”, and the latch of the registerselected by the counter is placed in the second signal state,thereafter, storing the column address in the register, and thereafter,making an increment of the column address and the counter; and

[0075] carrying out the above operations until the counter has reachedan end column address.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0076]FIG. 1 is a block diagram showing a schematic configuration of aNAND type flash memory according to the present invention;

[0077]FIG. 2 is a circuit diagram showing a configuration of a part of amemory cell array of the memory shown in FIG. 1;

[0078]FIG. 3 is a flowchart showing a wafer test step of the memoryshown in FIG. 1;

[0079]FIG. 4 is a circuit diagram showing a specific configuration of atimer circuit 22 shown in FIG. 1, a trimming data register 23, and acircuit in a control circuit 25 relating to these circuits;

[0080]FIG. 5 is a timing chart showing an example of operation of thecircuit shown in FIG. 4;

[0081]FIG. 6 is a circuit diagram showing a specific example of areference clock generator circuit 22B shown in FIG. 4;

[0082]FIG. 7 is a circuit diagram showing an exemplary specificconfiguration of a variable resister circuit R shown in FIG. 6;

[0083]FIG. 8 is a circuit diagram showing a detailed configuration of atrimming data register 23 shown in FIG. 4;

[0084]FIG. 9 is a view showing a relationship between data in theregister 23 shown in FIG. 8 and a deviation (ΔTint) of a time TINT;

[0085]FIG. 10 is a view showing a sequence during trimming of the timercircuit 22 shown in FIG. 4;

[0086]FIGS. 11A and 11B are views showing timing charts during trimmingof the timer circuit 22 shown in FIG. 4;

[0087]FIG. 12 is a flowchart showing operating procedures when aregister control command is supplied to an I/O buffer 16 shown in FIG.1;

[0088]FIG. 13 is circuit diagram showing a schematic configuration of aninternal voltage generator circuit 20 shown in FIG. 1, a trimming dataregister 21, and a circuit in a control circuit 25 relating to thesecircuits;

[0089]FIG. 14 is a view showing a correlation between data stored in theregister 21 in the circuit shown in FIG. 13 and a reference voltageVref;

[0090]FIG. 15 is a view showing a test sequence of the circuit shown inFIG. 13;

[0091]FIG. 16 is a circuit diagram showing a circuit at a portionrelating to generation of a non-selective cell word line voltage Vreadof the internal voltage generator circuit 20 shown in FIG. 1 and acircuit in a control circuit 25 relating to these circuits;

[0092]FIG. 17 is a view showing a relationship between the trimmingcount when trimming of each voltage is carried out and a voltage aftertrimming;

[0093]FIG. 18 is a circuit diagram showing an outline of part of amemory cell array 11 and a page buffer 13 shown in FIG. 1;

[0094]FIG. 19 is a circuit diagram showing a configuration of a circuitrelating to column redundancy in the memory shown in FIG. 1;

[0095]FIG. 20 is a circuit diagram showing a circuit configuration ofone unit of a defective column address register 19 shown in FIG. 19;

[0096]FIG. 21 is a flowchart showing sequences for defective columndetection and replacement in the memory shown in FIG. 1;

[0097]FIG. 22 is a flowchart showing a step of column check of aredundancy region in the memory shown in FIG. 1;

[0098]FIG. 23 is a flowchart showing sequences ofopen-circuit/short-circuit/leak defect detection/replacement in thememory shown in FIG. 1;

[0099]FIG. 24 is a flowchart showing an operation for detecting andregistering a column with its open-circuit defect, of a column of aredundancy region in the memory shown in FIG. 1;

[0100]FIG. 25 is a flowchart showing a defect detection/replacementoperation in the memory shown in FIG. 1;

[0101]FIG. 26 is a flowchart showing a sequence for searching a normalmemory block in the memory shown in FIG. 1;

[0102]FIG. 27 is a flowchart showing a sequence for Vpgm initial valuetrimming in the memory shown in FIG. 1;

[0103]FIG. 28 is a view showing how a writing voltage Vpgm changes inthe sequence shown in FIG. 27;

[0104]FIG. 29 is a circuit diagram showing a configuration of a circuitrelating to a block defect detection system shown in FIG. 1;

[0105]FIG. 30 is a flowchart showing procedures for defective blockdetection shown in FIG. 1;

[0106]FIG. 31 is a flowchart showing procedures for “1” data readoutcheck during defective block detection;

[0107]FIG. 32 is a flowchart showing procedures for readout check of aphysical checker pattern during defective block detection;

[0108]FIG. 33 is a flowchart showing a sequence for counting the numberof flags for a defective block after defective block detection;

[0109]FIG. 34 is a view illustrating a testing method according to asecond embodiment of the present invention; and

[0110]FIG. 35 is a flowchart showing an outline of a conventional wafertest step.

DETAILED DESCRIPTION OF THE INVENTION

[0111] Hereinafter, preferred embodiments of the present invention willbe described with reference to the accompanying drawings.

[0112]FIG. 1 is a block diagram showing a schematic configuration of aNAND type flash memory formed on a semiconductor chip according to thepresent invention. FIG. 2 is a circuit diagram showing a configurationof part of a memory cell array in the memory shown in FIG. 1. FIG. 3 isa flowchart showing a wafer test step in the memory shown in FIG. 1.

[0113] In FIG. 1, a memory cell array 11 is configured so that anonvolatile memory cell (not shown) capable of being electricallyrewritten is arranged in column and row directions in matrix. The abovenonvolatile memory cells each have a stack gate type MOS transistorstructure having a control gate and a floating gate laminated thereon.

[0114] Here, the memory cell array 11 is formed a well regioninsulated/separated from another region. When memory cell data in thememory cell array 11 is erased, there is employed an erasing method suchthat erasure operation is divided into a plurality of steps, thereby tobe associated with a step sequence, and an erasure voltage assigned inthe above well region is increased from an initial voltage by apredetermined voltage.

[0115] In addition, a redundancy column replaced with a defective cellfor use is provided in the memory cell 11. Further, an initializationdata region for storing initialization data is set in the memory cellarray 11.

[0116] In the memory cell array 11, a plurality of word lines WL and aplurality of bit lines BL are provided so as to cross each other, and aplurality of word lines are selectively driven by a decode output of arow decoder 12. During data readout, the data read out from the memorycell in the memory cell array 11 is supplied to a page buffer 13 via thebit line BL, and is sensed here. The data sensed by the page buffer 13is selected in units of columns by a column gate circuit 14 to besupplied to an I/O bus 15, and further, is outputted from an I/O buffer16 to the outside of a semiconductor chip. During data writing, incontrary to the above, the write data supplied from the outside of thesemiconductor chip is supplied to the column gate circuit 14 via the I/Obuffer 16 and the I/O bus 15. In this manner, a voltage according towrite data is supplied to the bit line BL via the page buffer 13, anddata is written into a selected memory cell.

[0117] In addition, to the above I/O buffer 16, the above write data issupplied from the outside of the chip during data writing, and a commandfor controlling an address for selecting a memory cell or memoryoperation is supplied. An address is captured in an address buffer 17,and a command is captured in a command buffer 18. A row address of theaddresses captured in the access buffer 17 is supplied to the rowdecoder 12, and a column address is supplied to the column gate circuit14.

[0118] In the case where a defective column exists in the above memorycell 11, a defective column address register (Bad Column Add. Register)19 for storing an address corresponding to such a defective column or adefective column address is provided. That is, the defective columnaddress register 19 is a register that stores an address of a defectivecolumn to be replaced with a spare column (that is, to be redundancyreplaced). In a memory according to the present embodiment, a defectiveblock is detected, and a flag is set so that a defective block/addresscan be identified by a user. Faulty block flag information is stored ina latch in the row decoder 12. This defective column address register 19is connected to the above I/O bus 15.

[0119] An interval voltage generator circuit 20 generates a variety ofvoltages for use in chips. This voltages include Vref (referencevoltage), Vpgm (writing voltage), an internal fall voltage (Vdd), anerasure voltage (Verase), a non-selected cell word line voltage (Vread)supplied to a non-selected cell word line and the like. A variety ofvoltages generated by the internal voltage generator circuit 20 issupplied to the row decoder 12 or the like.

[0120] A trimming data register (Trim. Data Register) 21 storesadjustment data (trimming data) for used in chips.

[0121] A timer circuit 22 generates a variety of timing pulses used whena variety of voltages are generated.

[0122] A trimming data register (Trim. Data Register) 23 storesadjustment data (trimming data) used when a variety of the above timingpulse is generated by the above timer circuit 22. In the above trimmingdata registers 21 and 23, when power is turned ON, data to be stored ina register are read out from an initialization data region describedlater in the memory cell array 11, and the read data are storedsequentially in the registers 21 and 23 each via the I/O bus 15.

[0123] An I/O control circuit (I/O Control) 24 captures a variety ofcontrol signals such as a chip enable signal /CE supplied from theoutside of a chip, a read enable signal /RE, a write enable signal /WEand the like. The control signal captured by the I/O control circuit 24and the command captured by the above command buffer 18 are supplied toa control circuit (Control Logic) 25.

[0124] The above control circuit 25 controls an operation of each of thecircuits inside the chips based on the result obtained by decoding thecontrol signal and command from the I/O control circuit 24. A variety ofregisters for storing control data are provided in this control circuit25. In addition, the control circuit 25 has a function for outputting aready/busy (R/Bn) indicating whether or not a chip is accessible to anexternal circuit.

[0125] In the memory array 11 shown in FIG. 2, for example, 16 memorycells are connected in series, thereby configuring a NAND cell unit. Aplurality of NAND cell units to which the work lines WL (WL0 to WL15)are connected in common configures a cell block that is a minimum unitof data erasure, and a plurality of cell blocks B0, B1, . . . , Bn aredisposed with the bit line BL being in common.

[0126] In the memory cell array 11, for example, the cell block Bn isused as an initialization data region for storing an initializationdata. This initialization data region enables data writing, erasure, andreadout by selectively driving the bit line BL and the word line WL.However, this region cannot be accessed from the outside in normalmemory operation. Therefore, the data in this initialization data regionis not erased during back data erasure or block unit erasure.

[0127] Now, an operation of each step during wafer test for a memoryhaving the above configuration will be described with reference to aflowchart shown in FIG. 3.

[0128] The wafer test comprises the following steps.

[0129] (1) DC test (DC Test)

[0130] (2) Default reset (Default Reset)

[0131] (3) Timer and voltage trimming (Timer & Voltage Trimming)

[0132] (4) Faulty column detection and replacement (Bad. Co. Detection &Repair)

[0133] (5) Searching a normal memory block (Good Block Search)

[0134] (6) Vpgm initial value trimming (Vpgm Initial Value Trimming)

[0135] (7) Faulty memory block detection (Bad Block Detection)

[0136] (8) Option set (Option Set)

[0137] (9) ROM fuse program (ROM-Fuse Program)

[0138] (10) Verification of register state when power is turned ON/OFF(Power Off, On Verification of Register State)

[0139] Of such wafer tests, the steps from (2) default reset to (9) ROMfuse program are continuously carried out without turning OFF the powerafter the power has been turned ON

[0140] Now, a description of each item will be given below.

[0141] (1) DC Test

[0142] First, DC test is carried out in the same way as in the priorart. Although this test cannot be carried out as automatic test, a rateof the test time to a total of test time is small, and thus, the testtime is not affected.

[0143] (2) Default Reset

[0144] All registers are set to default (initial) state after DC test.Although this test cannot be carried out as an automatic test, thetrimming data registers 21 and 23 are reset so that the storage value ofeach register is obtained as a default trimming value. On the otherhand, the defective column address register 19 and the defective blockflag is reset so that a defective column and a defective block do notexist.

[0145] (3) Timer and Voltage Trimming

[0146] This step carries out trimming of a pulse width of a pulse signalgenerated by the timer circuit 22 and trimming of a value of a voltagegenerated by the internal voltage generator circuit 20. The voltages tobe trimmed here include: a reference voltage Vref, an internal fallvoltage Vdd, and a non-selected cell work line voltage Vread.

[0147] Hereinafter, the testing methods are described for each item.

[0148] [Timer Trimming]

[0149]FIG. 4 shows a specific configuration of a circuit in a timercircuit 22 shown in FIG. 1, a trimming data register 23, and a controlcircuit 25 relating to these circuits.

[0150] The timer circuit 22 is composed of a timer signal generatorcircuit 22A and a reference clock generator circuit 22B.

[0151] The timer signal generator circuit 22A generates a pulse TMCLKfrom a basic clock PULSE generated by the reference clock generatorcircuit 22B, as shown in a timing chart of FIG. 5. Here, the above pulseTNINT is a pulse that corresponds to an integer product of the basicclock, and that is generated with a timer reset signal TMRST being atrigger. The pulse TMCLK is set to “H” after an elapse of time of TINTafter the pulse TMINT has been set to “H”. The pulse width (100 ms) ofthe time TINT and the pulse TMCLK is generated from the reference clock,and thus, increases or decreases according to a deviation of thereference clock.

[0152] The pulse TMCLK generated by the timer signal generator circuit22A is supplied to an AND gate 32 together with to a pulse TMEST havinga desired pulse width Text, the pulse TMEST being supplied to a chip pad(Pad) 31.

[0153] An output of the above AND gate 32 is supplied to a set terminalof a flip flop 33 of set/reset type. In addition, a timer reset signalTMRST is supplied to a reset terminal of the flip flop 33. An output ofthis flip flop 33 is supplied as a flag FLAG to a trimming data registercontrol circuit (Register Control) 34. This control circuit 34 suppliesan increment signal “inc” or a reset signal “rst” to the trimming dataregister 23 according to a state of the above flag FRAG.

[0154] A specific example of the above reference clock generator circuit22B is shown in a circuit diagram of FIG. 6. Here, two reference delaygenerator circuits 35A and 35B has a similar circuit configuration.These two circuits each are composed of: a differential amplifier 41;two N-channel MOS transistors 42, 43; a variable register circuit R thatchanges a resistance value between both terminals according to atrimming signal; a P-channel MOS transistor 44 and a capacitor C.Reference delay generator circuits 35A and 35B each generate a delaytime that corresponds to a product RC between a resistance value in thevariable resistor circuit R and a capacitance value of the capacitor C.

[0155] Outputs of both of the above reference delay generator circuits35A and 35B are supplied to a flip flop 45 that comprises two NANDcircuits together with a timer reset signal TMRRSTn. In one outputsignal of this flip flop 45, an AND logic with the timer reset signalTMRRSTn is obtained by an AND circuit 46, whereby a control signal DEN1is generated. This control signal DEN1 is supplied to a gate of theP-channel MOS transistor 44 in one reference delay generator circuit35B. In addition, in the other output signal of the above flip flop 45,an AND logic with the timer reset signal TMRRSTn is obtained by an ANDcircuit 47, whereby a control signal DEN0 is generated. This controlsignal DEN0 is supplied to a gate of the P-channel MOS transistor 44 inthe other reference delay generator circuit 35A, and is inverted by aninverter 48 to be obtained as a basic clock PULSE.

[0156] In the thus configured reference clock generator circuit 22B, inthe reference delay generator circuits 35A and 35B, the P-channel MOStransistor 44 is turned ON while the control signal DEN0 or DEN1 is setto “L”, and the capacitor C is charged by a power voltage. Here, when athreshold voltage of the N-channel MOS transistor 42 is defined as Vth,a voltage of a negative terminal of the differential amplifier 41 is setto Vth.

[0157] Next, when the control signal DEN0 or DEN1 is changed to “H”, theP-channel MOS transistor 44 is turned OFF, and charging of the capacitorC is not carried out. Here, the N-channel MOS transistors 42 and 43 eachconfigure a current mirror circuit. A current proportional to a currentthat flows the N-channel MOS transistor 42 via the variable registercircuit R flows the N-channel MOS transistor 43 as well, and thecapacitor C is discharged by this current. Then, if the terminal voltageof the capacitor C is lower than the voltage Vth of the negativeterminal of the differential amplifier 41, an output signal of thedifferential amplifier 41 is inverted from “H” to “L”. Then, a delaytime from when the control signal DEN0 or DEN1 is inverted from “L” to“H”, then to when the output of the differential amplifier 41 isinverted from “H” to “L” corresponds to the above product RC between theresistance value in the variable resistor circuit R and the capacitancevalue of the capacitor C. Such operation is repeated alternately by thetwo reference delay generator circuits 35A and 35B, whereby a basicclock PULSE having a period that is twice of the delay time RC isoutputted from the inverter 48. Here, the variable register circuit Rcan change a resistance value according to a value of a trimming signal,thus making it possible to adjust a reference delay time by means of atrimming signal. The reference clock generator circuit 22B is notlimited to that shown in FIG. 6. Any other circuit configuration may beused as long as a reference clock can be adjusted by a trimming signal.

[0158]FIG. 7 is a circuit diagram showing a specific, exemplaryconfiguration of the variable resistor circuit R shown in FIG. 6. Thisvariable resistor circuit R is composed of a decoder circuit 49; eightresisters R0 to R7 whose values are different from each other; and eightN-channel MOS transistors Q, each of which are connected in series toeach of these registers.

[0159] The above decoder circuit 49 decodes a 3-bit trimming signalTTMR0 to TTMR2, for example, and eight different decode signals areoutputted. Then, each of these eight different decode signals issupplied to a gate of each of these eight N-channel MOS transistors Q.

[0160] In the thus configured variable resistor circuit R, any one ofthe eight N-channel MOS transistors Q is turned ON based on the 3-bittrimming signals TTMR0 to TTMR2, whereby the resistance value betweenboth terminals (between both terminals of a serial circuit between eachof the resistors R0 to R7 and each of the eight N-channel MOStransistors Q) changes in eight different ways.

[0161]FIG. 8 shows a detailed circuit configuration of the trimming dataregister 23 shown in FIG. 4. This register 23 holds 4-bit data, forexample. This index bit serves as an index indicating whether or nottrimming test has been carried out. Remaining 3 bits TTMR0 to TTMR2 arenet trimming information.

[0162] As shown in FIG. 8, the counter configured of three D-type flipflops (DFF) 550 that have been connected in series is compatible with aregister that stores trimming information TTMR0 to TTMR2. The index bitis stored in a latch circuit (INDEX Latch) 51. The data contained ineach flip flop 50 and latch circuit 51 is inputted/outputted between theI/O bus 15 via each of two clocked inverters 52 and 52 provided for eachflip flop 50 and latch circuit 51, respectively.

[0163] When the data contained in the register 23 is written into amemory cell, the data is transferred to a page buffer 13 (shown inFIG. 1) via the I/O bus 15. In addition, when the data is transferredfrom the memory cell to the register 23 after power has been turned ON,the data is captured from the page buffer 13 to the register 23 via theI/O bus 15.

[0164]FIG. 9 shows a relationship in deviation (Δ TINT) between the data(TTMR0 to TTMR2 and INDEX) contained in the register 23 and the aboveTINT. The INDEX bit is set to “0” in a default reset state, and is setsuch that a deviation between each of TTMR0 to TTMR2 and TINT isobtained as 0%. When timer trimming test is started, the register datais set to its initial state. At this time, the INDEX bit is set to “1”.In the initial state, TTMR0 to TTMR2 are set to all “0”s.

[0165] Next, every time the increment signal “inc” is generated from thecontrol circuit 34 shown in FIG. 4, the data contained in TTMR0 to TTMR2are sequentially incremented. As shown in FIG. 9, the TINT time iscontrolled to be sequentially increased as TTMR0 to TTMR2 areincremented.

[0166] Trimming of the timer circuit can be done as follows by usingsuch register function and circuit configuration.

[0167]FIG. 10 shows a sequence during trimming of the timer circuit 22.FIGS. 11A and 11B show timing charts during trimming. FIG. 12 is aflowchart showing operating procedures when a register control commandis supplied to an I/O buffer 16 shown in FIG. 1. First, when a testingstart command is inputted, the register 23 is set to its initial stateso that the timer circuit 22 can be tested.

[0168] Next, a pulse TMEXT having a target width Text is inputted to apad 31 shown in FIG. 4. In this manner, pulses TMRST, TMINT, and TMCLKare set with TMEXT being a trigger. Here, as shown in FIG. 11A, when thepulse TMCLK is set while TMEXT is set to “H”, FLAG becomes “H”. As shownin FIG. 11B, when the pulse TMCLK is set while TMEXT is set to “L”, theflag FLAG becomes “L”.

[0169] Next, a register control command is inputted. When this commandis inputted, when FLAG is set to “H”, the control circuit 34 generatesan increment signal “inc”. If FLAG is set to “L”, the increment signal“inc” is not generated. The register control command may be formed asgeneral command input or a /WE signal toggle.

[0170] When testing is carried out in accordance with the sequence shownin FIG. 10, while Tint<Test, the register data are sequentiallyincremented, and the timer times sequentially increases. At a stage whenTint>Text, the data are not incremented. Therefore, at a time when atesting end command is supplied, and the sequence terminates, theregister data is set to a value such that Tint and Text aresubstantially equal to each other.

[0171] Although a target value of a basic clock pulse width is 100 ms,the TINT time is set to 100 microseconds, for example, which issufficiently longer than the target value. This is because an effectcaused by a logic delay occupied in TINT is sufficiently reduced.

[0172] Now, a flowchart shown in FIG. 12 will be briefly described.

[0173] When a test command is supplied (command input), an R/Bn(ready/busy) signal is set to “L” at the step S1 (R/Bn=“L”), and it isnotified to the outside that the chip is in a busy state. Next, at thestep S2, it is judged whether or not the flag FLAG is set to “H”(FLAG=“H”?). At this time, when the flag FLAG is not set to “H”, thepulse width of the basic clock has already been to set to a targetvalue. Then, a status (Status) is set to a pass (Pass) state(Status=“Pass”), the R/Bn signal is set to “H”, and timer trimming testoperation terminates.

[0174] On the other hand, when it is judged that the flag FLAG is set to“H” at the step S2, it is judged whether or not trimming data reaches amaximum at the next step S3 (Trim. Data=Max?). When the data has alreadyreached the maximum, the register 23 is reset at the step S4 (RegisterReset). Then, a status is set to a fail (Fail) state (Status=“Fail”)that indicates that trimming has failed, the R/Bn signal is set to “H”,and timer trimming test operation terminates.

[0175] When it is judged that the trimming data does not reach themaximum at the step S3, data contained in the register 23 is incrementedat the next step S5 (Increment Register Data). Then, a status is set toa fail state (Status=“Fail”), the R/Bn signal is set to “H”.

[0176] The above described testing method has the following advantages.

[0177] (1) A tester may only input a common command to each chip. Inparticular, it is required to carry out computation for determiningtrimming data by using the tester's CPU.

[0178] (2) In addition, the tester may not have a memory for storingcharacteristic data for each chip

[0179] These facts denotes that testing can be carried out completely inparallel to about 100 chips. In addition, they means that trimming testcan be done even by using a tester with high performance or highcapability. Therefore, as compared with a conventional testing method, atest time can be significantly reduced, and a testing cost can besignificantly reduced.

[0180] Here, a trimming test of the timer circuit 22 has been described.As described hereinafter, the essence of this test is applicable tovoltage trimming or redundancy computation as well.

[0181] In addition, although this system assumes a memory capable ofwriting trimming data into the memory cell array 11, the system isapplicable to a memory having trimming data stored in a laser fuse aswell. In that case, after trimming data has been determined with theabove described method, the data contained in the registers 21 and 31are moved to the tester memory, and then, fuse cutting may be carriedout based on the data. In this case, although the above advantage of (2)is lost, the above advantage of (1) is maintained, thus making itpossible to reduce a test time.

[0182] [Voltage Trimming]

[0183] Voltages for use in chips each can be carried out in the same wayas when trimming of the above timer circuit 22 is carried out.

[0184]FIG. 13 shows a specific configuration of an internal voltagegenerator circuit 20 shown in FIG. 1, a trimming data register 21, and acircuit in a control circuit 25 relating to these circuits. Now, adescription will be given by way of example of generating a referencevoltage Vref.

[0185] The internal voltage generator circuit 20 is composed of: adivider circuit supplied to a pad 61 (Monitor PAD) from the output ofthe reference voltage Vref or chip generated by this internal voltagegenerator circuit 20, the divider circuit consisting of a variableresistor circuit 62 and a resistor 63 connected, the divider circuitresistance-dividing a reference voltage that corresponds to a desiredreference voltage; a comparator 65 that compares a BGR voltage Vgrgenerated by a band gap type constant voltage generator circuit (BGRCircuit) 64 with a voltage divided by the divider circuit that comprisesthe above variable resistor circuit 62 and resistor 63; a flag generatorcircuit 66 that generates the flag FLAG based on an output of thiscomparator 65 and a test signal VREFTEST; a switch circuit 67 thatcomprises two P-channel MOS transistors connected in series in order toconnect a node of the reference voltage Vref to a power voltage based onthe output of the comparator 65 and the test signal VREFTEST; and aregister control circuit (control) 68 that supplies an increment signal“inc” or a reset signal “rst” to the register 21 based on the above flagFLAG.

[0186] Here, the trimming signal outputted from the register 21 isobtained as 4 bits of TVREF0 to TVREF3, for example. A configuration ofthis register 21 may be similar to that of timer trimming. In thevariable resistor circuit 62, a resistance at both ends of the circuitchanges according to the above 4-bit trimming signals TVREF0 to TVREF3.This variable resistor circuit 62 may be configured in the same way asthat shown in FIG. 7. However, in this case, a decoder circuitcorresponding to the decoder circuit 49 outputs 16 different decodesignals according to a 4-bit trimming signal. 16 resistors correspondingto the resistors R0 to R7 are provided, and 16 MOS transistorscorresponding to the N-channel MOS transistors Q as well are provided.

[0187]FIG. 14 shows a correlation between data stored in the register 21and a reference voltage Vref in the circuit shown in FIG. 13. Further,FIG. 15 shows a test sequence of the circuit of FIG. 13.

[0188] As shown in FIG. 15, when trimming of the reference voltage Vrefis carried out, a reference voltage is first inputted to a pad 61.Subsequently, when a testing start command is inputted, the test signalVREFTEST shown in FIG. 13 is set to “H”, and the switch circuit 67 isturned OFF. Then, the reference voltage inputted to the pad 61 isdivided by the divider circuit that comprises the variable resistorcircuit 62 and resistor 63, and the divided voltage is compared with theBGR voltage Vbgr generated in the chip by the comparator 65. Inaddition, when the test signal VREFTEST is set to “H”, the flaggenerator circuit 66 is operable, and the comparison result of thecomparator 65 is reflected on the flag FLAG.

[0189] Here, the register data and output voltage (Vref) have arelationship as shown in FIG. 14. While the output voltage Vref issmaller than its target value, the register data is incremented (inc)every time a register control command (B in FIG. 15) is inputted. Then,at a time when the output voltage Vref is greater than the target value,incrementing stops. In this way, as in timer trimming, voltage trimmingcan be done by a complete parallel test.

[0190] Trimming of the internal fall voltage Vdd as well can be donewith the circuit and method similar to that of the reference voltageVref.

[0191] As shown in FIG. 15, instead of inputting a register controlcommand B from the outside, a register control operation may be carriedout automatically by using the timer circuit 22 and control circuitinside the chips.

[0192] On the other hand, in the case of trimming a rise voltage such asnon-selected cell word line voltage Vread, the circuit having theconfiguration as shown in FIG. 16 is used. That is, FIG. 16 shows acircuit at a portion relating to generation of a non-selected cell wordline voltage Vread of the internal voltage generator circuit 20 shown inFIG. 1 together with a trimming data register 21 and a circuit in thecontrol circuit 25 relating to these circuits.

[0193] A non-selected cell work Vread is generated by a voltage risecircuit (Vread Charge Pump) 71. The voltage Vread generated by thisvoltage rise circuit 71 and the reference voltage supplied from theoutside of the chip, the reference voltage corresponding to a desirednon-selected cell word line voltage, are resistance-divided by a dividercircuit that comprises a variable register circuit 73 and a resistor 74that are connected in series. The above divided voltage VMON is comparedwith the reference voltage Vref by a comparator 75. An output of thiscomparator 75 is inverted by an inverter 76, and the inverted output issupplied as a flag FLAG to a register control circuit 68. This registercontrol circuit 68 supplies an increment signal “inc” or a reset signal“rst” to the register 21 based on the above flag FLAG.

[0194] When a testing start command is inputted while a referencevoltage is inputted to a pad 72, a voltage rise circuit 71 is placed inan inactive state based on a disable signal “disable”, and further, thecomparator 75 is placed in an active state based on an enable signal“enable”. Then, the reference voltage inputted to the pad 72 isresistance-divided by means of a divider circuit that comprises thevariable resistor circuit 73 and resistor 74, and the divided voltage iscompared with the reference voltage Vref by the comparator 75. Theincrement signal “inc” or reset signal “rst” are supplied from theregister control circuit 68 to the register 21 according to the flagFLAG generated based on the comparison result.

[0195] As shown in FIG. 16, a parasitic resistance Rpad associated withwiring exists between the pad 72 and the variable resistor circuit 73.When this parasitic resistance Rpad is great, even if a correctreference voltage is inputted to the pad 72, the voltage after trimmingis shifted. In such a case, a higher reference voltage may be inputtedin advance to the pad 72 so that a value of Rpad is nor affected by suchshifting. This input is effective in reference voltage inputted from thecorresponding pad during trimming of the reference voltage Vref andinternal fall voltage Vdd.

[0196]FIG. 17 shows a relationship between trimming count and voltageafter trimming when trimming of each voltage is carried out as describedabove. In the case where trimming of each voltage is carried out, apredetermined dispersion occurs at the initial voltage of each chip, asshown in FIG. 17, depending on conditions such as manufacturing process(Initial Distributing). For example, if the initial voltage of a chip Ais higher than that of a chip B, a dispersion of stepping voltage Vstepper step occurs between the chips A and B at a time when trimmingterminates (Final Distributing).

[0197] Then, a voltage lower than a target value by Vstep/2, namely, avoltage obtained by target value −Vstep/2 is inputted as a referencevoltage inputted to the pad during trimming, the voltage after trimmingjust coincides with a target value, and a dispersion does not occurbetween chips. Conversely, the target value may be a voltage higher thana reference voltage Vpad inputted to the pad by Vstep/2 may be, namely,Vpad+Vstep/2.

[0198] (4) Faulty Column Detection and Replacement

[0199] Conventionally, defective column detection has been carried outafter a memory block (Good Block) has been detected, and trimming of theVpgm initial value has been carried out.

[0200] However, there may occur a circumstance that, if a defectivecolumn exists, a normal memory block does not exist in a semiconductorchip. This is because, although whether or not a normal memory blockexists is judged according to whether or not writing/erasure is carriedout, and thereafter batch sensing is passed for check, if a defectivecolumn exists, the result is always “fail” (Fail) during batch sensing.

[0201] Because of this, in a memory according to the present embodiment,normal memory block search (Good Block Search) is carried out afterdefective column detection and replacement of a detected defectivecolumn with a redundancy column, and trimming of the Vpgm initial valueis carried out.

[0202] In order to carry out defective column detection and replacementwith a redundancy column prior to carrying out trimming of the Vpgminitial value, it is required to detect a defective column by making abit line leak check or an open-circuit check and the like. Conversely, adefective column can be detected by such a technique, thus making itpossible to bring the step of defective column detection prior to thestep of Vpgm initial value trimming.

[0203] A specific method of defective column detection/replacement willbe described below. First, a configuration of a circuit concerningdefective column detection/replacement will be described here.

[0204]FIG. 18 shows an outline of part of the memory cell array 11 andthe page buffer 13 shown in FIG. 1. Here, one page of the memory cellarray 11 comprises 1,056 bytes=1024+32. Data is inputted/outputted inunits of bytes, and thus, a column address has 11 bits from A0 to A10. Adefective column in a main region is replaced with a column redundancyin units of bytes. The column redundancy has 8 bytes for one plane. Inaddition, two bit lines BL are assigned to one page buffer (PB). Aconnection line is determined depending on signal lines BLTRe, BLTRo,BLCUe, and BLCUo. For example, when BLTRe=“H”, and BLTRo=“L”, an evennumber bit line BL is connected to the page buffer PB. At this time, thesetting is BLCUe=“L” and BLCUo=“H”, and a non-selected bit line BL isconnected to aground (gnd). An even number bit line and an odd numberbit line are regarded as belonging to separate pages.

[0205]FIG. 19 shows a configuration of a circuit relating to a columnredundancy in the memory shown in FIG. 1. At a stage when operations fordefective column detection and replacement complete, a defective columnaddress is stored in the defective column address register 19. If acolumn address inputted to the column address buffer 17A that is a partof the address buffer 17 coincides with an address in the defectivecolumn address register 19, a main column region is non-selected, and aredundancy region is selected.

[0206] During readout operation, data contained in the selected eight(one byte) page buffers PB are outputted to the I/O bus 15 via a buffercircuit (Buffer) 81. When write data is inputted (data load) in the pagebuffer PB, data is transferred in a path which is reversed from theabove.

[0207] A signal line LSENLR shown in FIG. 19 is used during batchsensing operation. At this time, in order to ensure that a defectivecolumn or information contained in a column redundancy region is notreflected in batch sensing operation, it is required to interrupt asignal path between these page buffers PB and the signal line LSENLR. Anisolation latch circuit (Isolation Latch) 82 provided for each of theeight page buffers PB is intended to store information indicatingwhether or not the above signal path is interrupted.

[0208] In FIG. 19, reference numeral 83 denotes a judgment circuit(Decision Circuit) for judging data outputted to the I/O bus 15 via thebuffer circuit 81; reference numeral 84 denotes a control circuit(Control); and reference numeral 85 denotes a register counter (RegisterCounter).

[0209]FIG. 20 shows a circuit configuration in one unit of the defectivecolumn address register 19 shown in FIG. 19. One of the defective columnaddresses A0 to A10 is stored in a circuit in unit o such one unit, anda latch circuit 91 for 11 bits is included. Whether or not the columnaddress inputted to the column address buffer 17A coincides with anaddress stored in the defective column address register 19 is judged bymeans of an EX-OR circuit (exclusive logical summation circuit) 92provided for each of the 11 latch circuits 91. A latch circuit 93 storesan index pit (INDEX). This index bit serves as an index for judgingwhether or not data stored in another 11 latch circuits 91 is valid. Inthe case where data “1” is stored in the latch circuit 93, it indicatesthat the data contained in the latch circuit 91 is a defective columnaddress. In the case where data “0” is stored, it indicates that thedata contained in the latch circuit 91 is invalid.

[0210] An output of the above EX-OR circuit 92 is inputted in parallelto a NOR circuit 94. An output of this NOR circuit 94 is inputted to aNAND circuit 95, and further, the data stored in the above latch circuit93 is supplied to this NAND circuit 95. Reference numerals 96 and 97each denote a decoder, and reference numerals 98 and 99 each denote aNAND circuit. A detailed description of the circuit shown in FIG. 20will be given later.

[0211] Now, a sequence for defective column detection and replacementwill be described here.

[0212]FIG. 21 is a flowchart of a defective column detection andreplacement sequence. This step has the following six portions.

[0213] (1) Column Redundancy Register Reset (Column, R/D Register Reset)

[0214] This step resets all defective column address registers. Inaddition, an index latch circuit are set to all “0”s.

[0215] (2) Redundancy Region Column Check (R/D Area Co. Check)

[0216] A defective column in a redundancy region is detected prior todetecting a defect in a main column region so that a defectiveredundancy column is not selected. This step comprises four steps asshown in FIG. 22.

[0217] (2-1) Open-Circuit Check Read (Open Check Read)

[0218] This step carries out readout (reading) for detecting anopen-circuit defect with a bit line. Thus, all the blocks arenon-selected, and reading is carried out while the gates of thetransistors connected to BLCUe and BLCUo shown in FIG. 18 areopen-circuited altogether. If a bit line BL is cut in a memory cellarray 1, data “0” (corresponding to a cell placed in an OFF state) isread out in the page buffer PB. If not, data “1” (corresponding to acell placed in an ON state) is read out. The readout time is set to beshorter than during reading for normal operation in order to detect astate in which a bit line BL is almost cut, and enters a highresistance. This read operation is read for all the bit lines of evennumber (even) and odd number (odd) at the same time. Thus, readout isfirst carried out for an even number bit line, and then, readout iscarried out an odd number bit line.

[0219] (2-2) Faulty Redundancy Column Detection (Bad R/D Col. Detect)

[0220] An open-circuit defect column of the columns in a redundancyregion is detected and registered. The flowchart of this operation isshown in FIG. 24. First, a command is inputted so as to enable directaccess to a column redundancy region (step S11). In this manner, asignal RDAC shown in FIG. 20 is set so as to enable selection of acolumn redundancy in the least significant 3 bits A0 to A2 in the columnaddress. Namely, the signal RDAC is set to “H”, whereby an output of aNAND circuit 98 is determined according to an output of a decoder 97 fordecoding the least significant 3 bits A0 to A2 of the column address,and further, a redundancy signal RDHITi is set via a NAND circuit 99.

[0221] Subsequently, a test command TR1 is inputted (step 12). TR0 is atest command that detects whether or not the page buffer data in theredundancy region are set to all “0”s. TR1 is a test command thatdetects whether or not the page buffer data in the redundancy region areset to all “1”s. The expected values (exp-val) of the page buffer datawhen the test command TR0 is inputted are set to all “0”s. The expectedvalue (exp-val) of the page buffer data when the test command 1 isinputted are set to all “1”s. In the flowchart shown in FIG. 24, thethick arrow represents a transition caused by external command input,and represents automatic transition caused by a control circuit in achip.

[0222] When a command is inputted, an R/Bn (ready/busy) signal is set to“L” at the step S13. Then, the column address buffer 17A and registercounter 85 shown in FIG. 19 are reset. In the column address buffer 17A,A0, A1, and A2 are set to “0”s, and the remains are reset to all “1”s(“00011 . . . 1”).

[0223] Next, the page buffer data in the selected redundancy istransferred to a judgment circuit 83 via a buffer circuit 81 shown inFIG. 19, and it is judged whether or not the data are set to all “1”s(step S14). If the judgment result is negative, it denotes that anopen-circuit defect occurs with such column, and the column cannot beused as a redundancy.

[0224] In this case, at the next step S15, the data contained in thecolumn address buffer 17A is stored in the latch circuit 91 in a circuitin one unit in a defective column address register 19 selected by theresistor counter 85, and an index bit (INDEX) of the latch circuit in acircuit for one unit is set to “1”. The thus stored address (all “1”sother than A0, A1, and A2) does not actually exist in a memory cellregion. Therefore, even if any address is inputted in the column addressbuffer 17A during normal operation, such address is not replaced withthis column redundancy.

[0225] On the other hand, if the judgment circuit 83 judges that all“1”s are set, the column address buffer 177A and register counter 85 areincremented altogether at the next step S16, and the next columnredundancy is selected. The above operation is repeated to the lastcolumn redundancy. When it is judged that processing reaches the lastcolumn redundancy at the step S17, the sequence terminates.

[0226] (2-3) Short/Leak Check Read (Short/Leak Check Read)

[0227] This step carries out reading for detecting a defect due toshorting or leakage between bit lines. Thus, all blocks arenon-selected, and reading is carried out. The read time is set to belonger than that of normal operation in order to provide a margin.

[0228] If a column is normal, data “0” is read out in a page buffer. Ifa short-circuit or leakage occurs, data “1” is read out.

[0229] (2-4) Faulty Redundancy Column Detection (Bad R/D col. Detect)

[0230] This step detects and registers a short-circuit or leakage defectcolumn of the columns in the redundancy region. If the column is normal,the data “0” should be inputted in a page buffer (expected value“xp-val.=All “0”), and thus, a command TR0 is inputted. The contents ofsequence is similar to those of the above item (2-2).

[0231] After the above operation has terminated, even and odd of a bitline is inverted, and operation similar to (2-1) to (2-4) is repeated.The even and odd of the bit line can be specified by a dedicatedaddress.

[0232] (3) [Data Input/Output Check Relevant to Page Buffer inRedundancy Region (R/D Area P/B Din/Dout Check)]

[0233] Data loading and data readout are carried out for a page bufferin a redundancy region, thereby checking that a page buffer logiccircuit is free of a defect (stuck-at-defect). Specifically, data “1” isfirst loaded in all the page buffers. Then, operation similar to (2-2)shown in FIG. 22 is made, thereby detecting/registering a defect. Next,data “1” is loaded, and operation similar to (2-4) shown in FIG. 22 ismade.

[0234] At the foregoing step, all the defective columns in theredundancy region are assumed to have been detected/registered. For aregister in a redundancy judged as a defect, “1” is set to INDEX.

[0235] (4) [Main Area Column Check (Main Area Col. Check)]

[0236] Next, a defective column in a main region is detected, and isreplaced with a redundancy column. First, detection. replacement of anopen-circuit defect and short-circuit/leakage defect (Bad ColumnDetection & Repair) is carried out. This sequence is shown in FIG. 23.The steps of open-circuit defective detection reading,short-circuit/leakage defect detection reading are completely identicalto that shown in FIG. 24.

[0237] A flowchart of defect detection/replacement operation is shown inFIG. 25. A command TR0 or TR1 is inputted according to whether anexpected value (xxp-va. “0” or “1” is detected (step S21).

[0238] Next, at the step S22, the setting is R/Bn=“L”, and the columnaddress buffer 17A and register counter 85 shown in FIG. 199 are reset.Then, in the column address buffer 17A, the starting address of the mainregion is selected. Next, at the step S23, data contained in the pagebuffer PB for each byte is detected (Byte by Byte comparison). If thedata contained in the page buffer PB is different from the expectedvalue, an index bit (INDEX) of the register selected at this time ischecked at the step S24. When INDEX=“0”, a defective address is storedin that register at the step S25, and the setting is INDEX=“1”.

[0239] At the step S24, when INDEX=“1”, it denotes that a defect occurswith a redundancy or that such redundancy is already used. At the stepS26, the register counter 85 is incremented. Then, at the step S27, aregister with INDEX=“0” is searched. If a register with INDEX=“0” doesnot exist after the counter has been incremented up, a flag “Fail” isset at a status (Status) latch at the step S28. After the end oftesting, the status latch state can be recognized by status latchreading.

[0240] On the other hand, when the data contained in the page buffer PBcoincides with the expected value at the step S23 and when the step S25terminates, the column address is incremented at the step S29. Then, atthe step S30, when redundancy replacement terminates normally (FinalCol. Add is detected), a flag “Pass” is set at a status latch at thenext step S31.

[0241] (5) [Data Input/Output Check Relevant to Page Buffer in MainRegion (Main Area P/B Din/Dout Check)]

[0242] Then, a defect with a page buffer logic circuit in a main regionis detected. Fault detection and replacement are carried out inaccordance with a flowchart shown in FIG. 25.

[0243] (6) [Setting Isolation Latch Circuit (Isolation Latch Set)]

[0244] After redundancy replacement has completed, an isolation latchcircuit 82 shown in FIG. 19 is set. First, a command is inputted, and anisolation latch reset signal “isolatrst” outputted from a controlcircuit 84 is set to “H”. In this manner, all the page buffers PB shownin FIG. 19 is isolated from a batch sensing line LSENLR. Next, anisolation latch enable signal “isolation” outputted from the controlcircuit 84 is set to “H”. In this state, data for one page is loaded.When a column is selected, data contained in the isolation latch circuit82 is inverted. An address for one page is scanned, whereby the settingof the isolation latch circuit 82 is completed.

[0245] An operation for defective column detection and replacement hasnow been completed. So far, a description has been given with respect toa case in which one memory plane is provided. In the case where aplurality of planes are provided, easy extension can be obtained.

[0246] Now, the step of (5) normal memory block search (Good BlockSearch) in a flowchart shown in FIG. 3 will be described here.

[0247] It is required to carry out a writing operation for determining aVpgm initial value in write erasable blocks. Then, normal memory blocksearch is carried out.

[0248] A sequence of this step is shown in a flowchart of FIG. 26.First, a proper initial block address is inputted (Input Initial BlockAddress). An initial block address may not be a starting block address.Next, a block erasure command is inputted, and this block is erased(Block Erase).

[0249] Following erasing operation, a erasure verification (checkingthat all “1”s are set by batch sensing) is carried out, and the resultis stored in a first status register provided at a control circuit 25 orthe like shown in FIG. 1.

[0250] Next, a manual program command (Manual Program) is inputted, andall “0”s are written into a selected page. In this manual program, thewrite loop count is defined as one, and Vrgm is defined as a maximumvalue or a value close to the maximum value. After programming, a verifyoperation is carried out, and the result is stored in a second statusregister provided in the control circuit 25 or the like (Manual All “0”Program (Vpgm fix)).

[0251] Subsequently, an address register control command is inputted(Input Address Register Control Command). In this manner, one or both ofthe contents of the above first and second status registers is “fail”(Fail), a block address is incremented. The contents of both of thestatus registers are “pass” (Pass), they are retained in that address.

[0252] As described above, instead of checking a status states of thefirst and second status registers, the above operation may be made byusing one status register such that the pass/fail results arecumulatively stored. That is, the result of immediately precedingerasure or write verification is “pass”, no register data is changed. Ifthe result is “fail”, a status register is provided such that a registerstate is forcibly set to a first signal state. In the case where thisregister data is “fail”, the block address is incremented. Iferasure/writing is carried out after this status register has been firstset to a “pass” state, when either of erasure and writing is “fail”,this register is placed in a “fail” state. Therefore, a function similarto the above can be achieved by one status register.

[0253] A sequence from block erasure to address register control commandinput is repeated in a predetermined number. As a result, at a time whenthe sequence terminates, an address of a normal memory block (GoodBlock) of each chip is entered in a block address buffer. This operationenables complete parallel operation as in the case of timer trimming orvoltage trimming. An address register control command serves as aregister control command in timer trimming or voltage trimming.

[0254] Next, the step of (6) Vpgm initial value trimming (Vpgm InitialValue Trimming) in the flowchart shown in FIG. 3 will be described here.

[0255]FIG. 27 is a flowchart showing a sequence for this Vpgm initialvalue trimming.

[0256] First, a register for storing a Vpgm initial value is reset (Vpgminitial Register Reset). This register functions as a counter in thesame way as the register shown in FIG. 8. When an increment signal isgenerated from a control circuit, the data contained in a register isincremented.

[0257] Next, a desired program loop count is inputted, and inputtedcount is stored in a predetermined register (Program Loop # Input). Whenan auto program (Auto Program) is executed, Vpgm is stepped up byinputted loop count. The pass/fail (Pass/Fail) information afterprogramming is stored in the second status register.

[0258] When a register control command is inputted at this stage (InputRegister Control Command), if a program status is “fail” (Fail), theregister value of the Vpgm initial value is incremented. When the statusis “pass” (Pass), the register state is maintained. Therefore, after agroup of the auto program and register control has been repeated in apredetermined number, the Vpgm initial value is inputted to the Vpgminitial value register such that writing terminates in a desired programloop count.

[0259]FIG. 28 shows how a writing voltage Vpgm changes in the abovesequence. Here, the program loop count is set to 5. In a first writesequence (Sequence), the Vpgm initial value is set to a minimum value.From the minimum value, the Vpgm value is stepped up 4 times (Step Up),then the status is judged. While the status is “fail” (Status Fail), theVpgm initial value is continuously incremented. When the status is“pass” (Status Pass), the Vpgm initial value keeps its state. Therefore,after this sequence has been repeated in a predetermined number, theVpgm initial value is set to an optimal value according to such chip.

[0260] During programming, a non-selected word line voltage Vpass aswell is stepped up.

[0261] The initial value of Vpass may be set so as to change togetherwith the Vpgm initial value.

[0262] Although a description has been given with respect to only amethod of optimizing the Vpgm initial value, the initial value of theerasure voltage Verase can be optimized in the similar way as required.

[0263] Now, the step of (7) defective memory block detection (Bad BlockDetection) in the flowchart shown in FIG. 3 will be described here.

[0264] In a NAND type flash memory, a flag FLAG (Bad Block Flag) is setto a defective block, and redundancy replacement is not carried out.Hereinafter, a sequence for detecting a defective block and setting aflag “Flag” will be described.

[0265]FIG. 29 shows a circuit configuration relating to a block defectdetecting system in FIG. 1.

[0266] In FIG. 29, reference numeral 101 denotes a defective block countcounter (Bad Block # Counter); reference numeral 17B denotes a rowaddress buffer that configures a part of the address buffer 17;reference numeral 102 denotes a block address pre-decoder (Blk AddressPreDecoder) that decodes an output of the row address buffer 17B; PBSBdenotes a wire; and reference numeral 103 denotes a control circuit thatdetects a signal of this wire, where an output of this control circuit103 and an output of a column gate circuit 14 via an I/O bus 15 aresupplied to the above defective block count counter 101 and row addressbuffer 17B.

[0267] Here, a partial decoder circuit 104 in number corresponding to amemory block in the memory cell array 11 is provided at the row decoder12. The partial decoder circuits 104 each comprises: a decoder circuit(Dec.) 105 that decodes an output of the above block address pre-decoder102; a level shift circuit (L/S) 106 that level converts an output ofthis decoder circuit 105, and supplies the converted output to thecorresponding memory cell block; a defective block flag register (BadBlock Flag Register) 107; a setter circuit 108 that comprises twoN-channel MOS transistors connected in series for setting this defectiveblock flag register 107 based on an output of the above decoder circuit105 and a flag register set signal FRSET; and a readout circuit 109 thatcomprises three N-channel MOS transistors connected in series forreading out the contents of the defective block flag register 107 basedon an output of the above decoder circuit 105 and a register sensesignal BLKSENS.

[0268] In addition, FIG. 30 is a sequence for defect block detection(Bad Block Detection). In FIG. 30, all 1 read check (Read All “1” Check)reads out and checks data “1” from all the memory cells. A checkerpattern (Checker Pattern) read check (Read “C” Check) reads out andchecks data when data “0” and data “1” are arranged in a lattice shape.Further, an inversion checker pattern check (Read “/C” Check) reads andchecks a checker pattern in which data “1” and data “0” arecomplementary to the checker pattern.

[0269] At a stage at which this detection test is carried out, a columnredundancy has already been replaced, and optimization of write erasurevoltage has been completed. Therefore, if readout data fails at thistime, such defect is regarded as a defective block. In this case, evenif a defect caused by a single cell, such defect is regarded as adefective block.

[0270] Hereinafter, a sequence operation will be described in order.

[0271] (1) Faulty Block Flag Register Reset (Bad Block Flag Reset)

[0272] All the defective block flag registers 107 are reset.

[0273] (2) Chip Erasure (Chip Erase)

[0274] Here, all cell data are erased. The chip erasing operation iscarried out by repeating block erasure in all blocks.

[0275] (3) Data “1” Readout Check (Read All “1” Check)

[0276] It is checked that cell data are placed in a erased state (“1”).First, an address of a starting block is specified, and the specifiedaddress is detected in accordance with the procedures shown in FIG. 31.The starting page is read, and batch sensing operation is made. If it isjudged that all “1”s are not set in batch sensing, a flag “fail” (Fail)is set at a status register. Then, a flag set command (Flag Set Command)is inputted. In this manner, if a status is “fail”, a flag is set at thedefect block flag register 107 that corresponds to the block. This flagis set by setting a signal FRSET shown in FIG. 29 to “H”. This operationis repeated for an even number page (Even Page) and an off number page(Odd Page), and then, a page address (Page Address) is incremented.Processing is terminated when the incrementing reaches the last page ofthe cell array.

[0277] (4) Physical Checker Pattern Program (Phys. “C” Program)

[0278] A physical checker pattern is written into all memory cells.

[0279] (5) Physical Checker Pattern Readout Check (Read All “C” Check)

[0280] A checker pattern is read in accordance with the procedures shownin FIG. 32. If a defect is detected, a flag is set at a defective blockflag register 107 that corresponds to that block. This operation isidentical to the above case of (3) except that read patterns aredifferent from each other. In a physical checker pattern, data “1” and“0” are written into an even number (Even) bit line and an odd number(Odd) bit line. Thus, for example, when an even number page (Even Page)is read out, all data “1” or “0” are read out. Therefore, a checkerpattern check can be made by utilizing batch sensing operation.

[0281] (6) Chip Erasure (Chip Erase)

[0282] All cell data are erased in the same manner as in the case of(2), and a pattern written in (4) is erased.

[0283] (7) Physical Checker Pattern (“/C”) Program (Phys. “/C” Program)

[0284] Physical checker pattern “/C” is written into all memory cells.

[0285] (8) Physical Checker Pattern Readout Check (Read All “/C”)

[0286] In the same manner as in the case of (5), “/C” is read. If adefect is detected, a flag is set at the block flag register 107 thatcorresponds to that block.

[0287] The upper limit of defective blocks in number is predetermined inaccordance with a specification. Thus, in order to check whether thenumber of defects detected by a sequence for defective block detection(Bad Block Detection), the flag counting sequence (Bad Block Flag #Count) of the defective flag shown in FIG. 33 is run. As to whether ornot a flag is set at the defective block flag register 107 thatcorresponds to a selected block, whether or not a wire PBUSB isdischarged may be detected by means of a control circuit 103 bypre-charging the wire PBUSB shown in FIG. 29 by thee control circuit103, and setting the register sense signal BLKSENS to “H”.

[0288] Now, the step of (8) option set (Option Set) in the flowchartshown in FIG. 3 will be described here.

[0289] By the foregoing operation, of the data stored in aninitialization data region of the memory cell array 11, informationconcerning a variety of trimming or a defective cell array section isdetermined. In the initialization data region, there is writteninformation concerning chip option (Option), for example, andinformation on whether or not chips are used as a multi-valued articleor a two-valued article and the like. Such information is inputted froma tester to each chip at this time. The inputted data is stored in apredetermined register.

[0290] Now, the step of (9) ROM fuse program (ROM-Fuse Program) in theflowchart shown in FIG. 3 will be described here.

[0291] Here, the data stored in each register are sequentiallytransferred to a page buffer, and then, the transferred data are writteninto an initialization data region. After writing has completed, poweris temporarily turned OFF, and is turned ON again. In a chip, power ONis sensed, data is read out from the initialization data region, and theread out data are sequentially transferred to each register. In thismanner, information concerning a variety of trimmings or a defectivecell array section is reflected on subsequent chip operation. Ifnecessary, a variety of voltages and timers are monitored in order tocheck this, and memory cell writing/erasing/readout operation is made.

[0292] Now, a second embodiment according to the present invention willbe described here.

[0293] Testing having all the same structures is carried out for timertrimming, voltage trimming, Vpgm initial value trimming, normal memoryblock search, and defective block detection of the above test steps.That is, first, a first command is inputted to carry out testing, andthe pass/fail information is outputted as a status or flag. Next, when asecond command is inputted, a group of the first command and secondcommand is repeated in a predetermined number, whereby informationaccording to characteristics for each chip can be acquired.

[0294] This method can be carried out by assigning a command to aplurality of chips. Thus, a complete parallel test can be carried out,and a test time can be reduced. In addition, there is no need to providea tester memory, and there is no need to make computation for dataacquired by the CPU in the tester, thus eliminating a high performancetester.

[0295] However, in the case of the above described timer trimming orvoltage trimming, it is required to repeat 2^(N) tests in order todetermine an N-bit register trimming value. Therefore, if N is greater,the test time is longer.

[0296] In such a case, the method described below is employed, therebymaking it possible to reduce the test time.

[0297]FIG. 34 shows how register data changes with this method when N=3.Hereinafter, a description will be given by way of example when timertrimming is carried out.

[0298] First, the register is set to (TTMR2, TTMR1, TTMR0)=(1, 0, 0),testing for comparing the previously mentioned Tint and Text with eachother, and TTMR2 at a third bit is set to “1” and “0”, respectivelyaccording to the result of “pass” (Tint>Text) and “fail” (Tint<Test).

[0299] Next, a second test is carried out by setting the remaining 2bits (TTMR1, TTMR0)=(1, 0), and a second bit is set. By doing this, asshown in FIG. 34, the third bit, second bit, and first bit aresequentially set through three tests.

[0300] By employing such a testing method, only N tests are required todetermine an N-bit register trimming value, and the test time can bereduced.

[0301] The present invention is not limited to the above describedembodiments each. At the stage of embodiment, various modifications canoccur without departing from the spirit of the invention.

[0302] As has been described, the semiconductor device and testingmethod are employed, whereby a complete parallel test can be carriedout, and the test time for the semiconductor storage device can bereduced. In addition, there is no need to provide a tester memory, andthere is no need to make computation for data acquired by the testerCPU. Thus, a high performance tester is eliminated, and the testing costcan be reduced. In addition, the testing method according to the presentinvention can be achieved merely by introducing a comparatively smallscale of circuits. Thus, a substantial increase in chip area due toemployment of this testing method does not occur.

[0303] In general, a wafer test sequence is optimized according toproduct properties. In the case of so called BIST (Built In Self Test),the testing step is incorporated in advance in a circuit, thus, makingit difficult to change a test sequence according to product properties.However, in the testing method according to the present invention, eachtest item is initiated by command input, and a test sequence with itsflexibility can be constructed. For example, in the case where there isa small amount of deviation in timer circuit, the timer trimming teststep may be deleted from the sequence. In addition, a defective addresscan be additionally registered with respect to a defective column or adefective block. Thus, a defect judged after a burn-in test has beencarried out, for example, can be saved.

[0304] In this way, the semiconductor device and testing methodaccording to the present invention are employed, making it possible toreduce the testing cost while maintaining flexibility in test sequence.

What is claimed is:
 1. A semiconductor device comprising: a bit line; aplurality of memory cells connected to said bit line; and a senseamplifier connected to one end of said bit line; and a defect detectorcircuit configured to read out data by said sense amplifier whilesetting a plurality of memory cells connected to said bit line all to anon-selected state, and the other end of said bit line being connectedto a predetermined potential via a switch, and an open-circuit defect ofsaid bit line being detected according to a readout data by said senseamplifier.
 2. A semiconductor device comprising: a memory cell array inwhich programmable and erasable nonvolatile memory cells are arranged incolumn and row directions of a matrix; an address register that canstore an address of a unit of memory cells which are programmed anderased simultaneously in said memory cell array; and a control circuitthat carries out an erase verify operation configured to output a “pass”or “fail” signal according to whether or not all said memory cellstargeted for erasing are erased, a write verify operation configured tooutput said “pass” or “fail” signal according to whether or not all saidmemory cells targeted for writing are written, and an operationactivated upon receipt of a first command, for, when either of resultsof said erase verify and write verify operations is “fail”, changingdata of said address register, and when said results are “pass”,disabling change of data of said address register.
 3. A semiconductordevice comprising a register activated by a command input, said registerhaving plural types of test operations configured to output a “pass” or“fail” signal, wherein, if a result of an immediately preceding testthat has been carried out of said test operations is “pass”, no data ischanged, and if said result is “fail”, data is set in a predeterminedsignal state.
 4. A semiconductor device having erase verify and writeverify functions comprising: memory cells; an address register that canstore an address of a unit of memory cells which are programmed anderased simultaneously in said memory cell array; a first register thatstores a “pass” and “fail” result after an erase verify operation; asecond register that stores a “pass” and “fail” result after a writeverify operation; a third register provided for each erase unit, saidthird register configured to store a first or second signal stateaccording to whether or not said memory cells in said erase unit arewrite-erasable or not; and a control circuit activated upon receipt of afirst command input, said control circuit making an operation such that,when at least one of said first register data and second register datais “fail”, a third register corresponding to an address selected by saidaddress register is set to a first signal state, and when both of saidfirst register data and second register data are “pass”, said thirdregister is set to a second signal state.
 5. The semiconductor deviceaccording to claim 4, further comprising a counter activated uponreceipt of a second command input, said counter counting said number ofthird registers set in a first signal state among all said thirdregisters.
 6. A semiconductor device comprising: an internal circuitwhose operation or function changes based on data stored in a register;and a control circuit that repeatedly makes a first operation to carryout a self-judgment test for said internal circuit such that a result ofeither of “pass and “fail” is outputted and a second operation to carryout a different control for said register according to said “pass” or“fail” result in said self-judgment test, wherein data reflecting saidcharacteristics of each semiconductor device is set to said register. 7.The semiconductor device according to claim 6, wherein said register hasa function for incrementing a data value upon receipt of a predeterminedsignal, and, when a result of said first operation is “fail” in saidsecond operation, said predetermined signal is generated, and when saidresult is “pass”, said predetermined signal is not generated.
 8. Thesemiconductor device according to claim 6, wherein said internal circuitis a timer circuit that generates a pulse whose pulse width is changedin accordance with data stored in said register, and said firstoperation is a self-judgment test that compares a pulse width of a pulseinputted from outside of said semiconductor chip with a pulse width of apulse generated by said timer circuit, and outputs “pass” or “fail”according to which of pulse widths is longer.
 9. The semiconductordevice according to claim 6, wherein said internal circuit is aninternal generator circuit that generates an internal voltage, saidvoltage value of said internal voltage is changed in accordance withdata stored in said register, and said first operation is aself-judgment test that compares a voltage inputted from outside of saidsemiconductor chip with said internal voltage generated by said internalvoltage generator circuit, and outputs “pass” or “fail” according towhich of said voltages is higher.
 10. The semiconductor device accordingto claim 9, wherein said internal voltage generator circuit comprises: avoltage generating section; a voltage dividing section that divides avoltage generated by said voltage generating section; and a comparatorthat makes a comparison of a voltage divided by said voltage dividingsection with a reference voltage, in which a result of said comparisonof said comparator is fed back to said voltage generating section tocontrol a voltage generating operation of said voltage generatingsection, wherein, during said self-judgment testing, said voltagegenerating section is placed in an inactive state, a voltage inputtedfrom outside of said semiconductor chip is inputted to said voltagedividing section to generate a divided voltage, and said “pass” or“fail” signal is generated according to said comparison result of saidcomparator in this state.
 11. The semiconductor device according toclaim 10, wherein said voltage generating section generates a voltagethat is higher by a predetermined value than an immediately precedingvoltage according to said data stored in said register, after a “fail”signal has been generated during said self-judgment test.
 12. Thesemiconductor device according to claim 11, wherein, during saidself-judgment test, a voltage lower than a desired voltage generated bysaid voltage generating section by ½ of said predetermined value isinputted from outside of said semiconductor chip and supplied to saidvoltage dividing section.
 13. The semiconductor device according toclaim 6, wherein said semiconductor device is a semiconductor memorycomprising memory cells each having a control gate and a floating gate,and when data is written into said memory cells, a writing voltageapplied to said control gate is increased from an initial voltage by apredetermined voltage each writing step; said internal circuit is awriting voltage generator circuit in which said initial voltage isdetermined in accordance with data stored in said register; said firstoperation is a self-judgment test in which “pass” or “fail” is outputtedaccording to whether or not all of said memory cells targeted forwriting are written after a predetermined times of writing operation;and said second operation is an operation in which, if a result of saidfirst operation is “fail”, said data stored in said register is changedto increase said initial voltage by a predetermined voltage, and if saidresult is “pass”, said data stored in said register is not changed. 14.The semiconductor device according to claim 6, wherein saidsemiconductor device is a semiconductor memory comprising memory cellsformed on a well region each having a control gate and a floating gate,and when data is erased from said memory cells, an erasing voltageapplied to said well region is increased from an initial voltage by apredetermined voltage each erasing step; said internal circuit is anerasing voltage generator circuit in which said initial voltage isdetermined in accordance with data stored in said register; said firstoperation is a self-judgment test in which “pass” or “fail”, isoutputted according to whether or not all of said memory cells targetedfor erasing are erased after a predetermined times of erasing operation;and said second operation is an operation in which, if a result of saidfirst operation is “fail”, said data stored in said register is changedto increase said initial voltage by a predetermined voltage, and if saidresult is “pass”, said data stored in said register is not changed. 15.The semiconductor device according to claim 6, wherein said registerstores a bit that indicates whether or not a test for determining datastored in said register is carried out.
 16. A semiconductor devicecomprising: an internal circuit in which an output is trimmed in 2^(N)different schemes by a register capable of holding N-bit data (where Ndenotes a positive integer); and a data setting circuit that judges in afirst test said output of said internal circuit while said N-bit data isplaced in a first state, to determine most significant bit data of saidN-bit data; judges, in a kth test (k=2, 3, . . . N), while data fromsaid most significant bit to a (k−1)th bit is maintained to a valuedetermined in a first to (k−1)th test, said output of said internalcircuit with said remaining bit being placed in a predetermined value todetermine a kth bit data; and sets data reflecting characteristics ofeach semiconductor device to said register by said N tests.
 17. Thesemiconductor device according to claim 16, wherein said register storesa bit that indicates whether or not a test for determining data storedin said register is carried out.
 18. A semiconductor device comprising:a memory cell array having a column region and a row region in whichmemory cells are arranged in column and row directions of a matrix; aredundancy column region having M redundancy columns for replacementwith a defective column in said memory cell array; M registersconfigured to store column addresses to be replaced with said redundancycolumns, each of said M registers including a latch placed to a first orsecond signal state according to whether or not a correspondingredundancy column can be used; a sense amplifier; a counter that selectssaid M registers sequentially; a judgment circuit that makes a judgmenton whether or not data of a selected column outputted from said senseamplifier coincides with a predetermined expected value and outputs a“pass” or “fail” signal according to a result of said judgment; and acontrol circuit that sets a column address and said counter to a startaddress, when a defective column in said memory cell array is to bedetected; makes, if an output of said judgment circuit is “pass”, anincrement of said column address, and, if said output of said judgmentcircuit is “fail” and said latch of said register selected by saidcounter is placed in said first signal state, stores said column addressin said register and thereafter making an increment of said columnaddress and said counter; makes an increment of said counter until saidcounter has reached a register whose latch is placed in said firstsignal state, if said output of said judgment circuit is “fail” and saidlatch of said register selected by said counter is placed in said secondsignal state, thereafter, stores said column address in said register,and thereafter, makes an increment of said column address and saidcounter, and performs said operations until said counter has reached anend column address.
 19. The semiconductor device according to claim 18,wherein said control circuit carries out an operation configured todetect a defect in said redundancy column region prior to an operationconfigured to detect a defective column in said memory cell array, andplaces said latch of said register in said second signal state, whichregister corresponds to a redundancy column in which a defect has beendetected, and sets a column address in said register not to select saidcolumn region of said memory cell array.
 20. A semiconductor devicecomprising: a memory cell array in which programmable and erasablenonvolatile memory cells are arranged in column and row directions of amatrix; a sense amplifier; a bit line extending in said columndirection, configured to transmit data of said memory cell array to saidsense amplifier; and a column defect detecting circuit that detects adefective column of said memory cell array, without carrying out writingand erasing operation for said memory cells.
 21. The semiconductordevice according to claim 20, wherein said column defect detectingcircuit detects a defective column in said memory cell array bydetecting whether or not an open-circuit, a short-circuit, or a leak arepresented in said bit line and said sense amplifier.
 22. Thesemiconductor device according to claim 21, wherein said column defectdetecting circuit reads out data by said sense amplifier while settingsaid memory cells connected to said bit line all to a non-selectedstate, said bit line being connected to a predetermined potential via aswitch, and detects an open-circuit defect of said bit line according toa readout data by said sense amplifier.
 23. A method of testing saidsemiconductor device claimed in claim 2, wherein a series of operationscomprising an erasing operation, an erase verify operation, a writingoperation, a write verify operation and said first command input arerepeated a plurality of times, to find a write-erasable region in amemory cell array.
 24. A method of testing said semiconductor deviceclaimed in claim 3, wherein plural types of said test operations arecarried out, and thereafter, it is judged whether or not said registerdata is set to a predetermined signal state to judge whether saidsemiconductor device is normal or defective.
 25. A method of testing asemiconductor device integrated on a semiconductor chip, saidsemiconductor device comprising a memory cell array that comprisesnonvolatile memory cells; a first register that stores an address of adefective region in said memory cell array; a plurality of internalvoltage generator circuits; and a second register provided correspondingto each of said plurality of internal voltage generator circuits, saidsecond register storing a trimming value for setting an internal voltagevalue generated by each of said internal voltage generator circuits,said semiconductor device being integrated on a semiconductor chip, saidmethod of testing a semiconductor device, comprising: resetting saidaddress of said defective region stored in said first register and saidtrimming value stored in said second register; and setting said addressof said defective region stored in said first register and said trimmingvalue stored in said second register to a value according to a propertyof each of said semiconductor chips, wherein said testing is carried outwithout turning a power supply off after said power supply has beenturned on.
 26. The method of testing a semiconductor device, accordingto claim 25, wherein said address of said defective region in saidmemory cell array is determined without outputting data stored in saidmemory cell array to outside of said semiconductor chip.
 27. The methodof testing a semiconductor device, according to claim 25, wherein saidtrimming value for setting said internal voltage value to be generatedby each of said internal voltage generator circuits is determinedwithout outputting said internal voltage value generated by said eachinternal voltage generator circuit to outside of said semiconductorchip.
 28. The method of testing a semiconductor device, according toclaim 25, wherein said address of said defective region stored in saidfirst register and said trimming value stored in said second registerare determined by an automatic testing activated by command inputs,respectively.
 29. The method of testing a semiconductor device,according to claim 25, further comprising writing which is performedfollowing said resetting of said address of said defective region storedin said first register and said trimming value stored in said secondregister which are set by said value according to said property of eachof said semiconductor chips, said address of said defective region andsaid trimming value into said nonvolatile memory cells of said memorycell array.
 30. A method of testing a semiconductor device integrated ona semiconductor chip, said semiconductor device comprising an internalcircuit in which an operation or function is changed based on datastored in a register, said method of testing a semiconductor device,comprises: a first operation configured to cause said internal circuitto carry out a self-judgment test such that a result indicating either“pass” or “fail” is outputted, and a second operation configured tocarry out for said register a control that is different depending onsaid result of “pass” or “fail” in said self-judgment test, wherein saidfirst operation and second operation are repeated alternately in apredetermined number of times to set for said register data reflectingcharacteristics of each of said semiconductor chips.
 31. The method oftesting a semiconductor device, according to claim 30, wherein saidregister stores a bit that indicates whether or not a test fordetermining data stored in said register is carried out.
 32. The methodof testing a semiconductor device, according to claim 30, wherein saidfirst operation and second operation are activated by correspondingcommand inputs, respectively.
 33. The method of testing a semiconductordevice, according to claim 30, wherein said register has a functionconfigured to increment a data value upon receipt of a predeterminedsignal, and said predetermined signal is generated when said result ofsaid first operation is “fail” in said second operation.
 34. The methodof testing a semiconductor device, according to claim 30, wherein saidinternal circuit is a timer circuit that generates a pulse whose pulsewidth is changed in accordance with data stored in said register, andsaid first operation is a self-judgment test that compares a pulse widthof a pulse inputted from outside of said semiconductor chip with a pulsewidth of a pulse generated by said timer circuit, and outputs “pass” or“fail” according to which of pulse widths is longer.
 35. The method oftesting a semiconductor device, according to claim 30, wherein saidinternal circuit is an internal generator circuit that generates aninternal voltage, said voltage value of said internal voltage is changedin accordance with data stored in said register, and said firstoperation is a self-judgment test that compares a voltage inputted fromoutside of said semiconductor chip with said voltage generated by saidinternal voltage generator circuit., and outputs “pass” or “fail”according to which of voltages is higher.
 36. The method of testing asemiconductor device, according to claim 35, wherein said internalvoltage generator circuit comprises: a voltage generating section; avoltage dividing section that divides a voltage generated by saidvoltage generating section; and a comparator that makes a comparison ofa voltage divided by said voltage dividing section with a referencevoltage, in which a result of said comparison of said comparator is fedback to said voltage generating section to control a voltage generatingoperation of said voltage generating section, wherein, during saidself-judgment testing, said voltage generating section is placed in aninactive state, a voltage inputted from outside of said semiconductorchip is inputted to said voltage dividing section to generate a dividedvoltage, and said “pass” or “fail” signal is generated according to saidresult of said comparator in this state.
 37. The method of testing asemiconductor device, according to claim 36, wherein said voltagegenerating section generates a voltage that is higher by a predeterminedvalue than an immediately preceding voltage according to said datastored in said register, after a “fail” signal has been generated duringsaid self-judgment test.
 38. The method of testing a semiconductordevice, according to claim 37, wherein, during said self-judgment test,a voltage lower than a desired voltage generated by said voltagegenerating section by ½ of said predetermined value is inputted fromoutside of said semiconductor chip and supplied to said voltage dividingsection.
 39. The method of testing a semiconductor device, according toclaim 30, wherein said semiconductor device is a semiconductor memorycomprising memory cells each having a control gate and a floating gate,and when data is written into said memory cells, a writing voltageapplied to said control gate is increased from an initial voltage by apredetermined voltage each writing step; said internal circuit is awriting voltage generator circuit in which said initial voltage isdetermined in accordance with data stored in said register; said firstoperation is a self-judgment test in which “pass” or “fail” is outputtedaccording to whether or not all of said memory cells targeted forwriting are written after a predetermined times of writing operation;and said second operation is an operation in which, if said result ofsaid first operation is “fail”, said data stored in said register ischanged to increase said initial voltage by a predetermined voltage. 40.The method of testing a semiconductor device, according to claim 30,wherein said semiconductor device is a semiconductor memory comprisingmemory cells formed on a well region each having a control gate and afloating gate, and when data is erased from said memory cells, anerasing voltage applied to said well region is increased from an initialvoltage by a predetermined voltage each erasing step; said internalcircuit is an erasing voltage generator circuit in which said initialvoltage is determined in accordance with data stored in said register;said first operation is a self-judgment test in which “pass” or “fail”is outputted according to whether or not all of said memory cellstargeted for erasing are erased after a predetermined times of erasingoperation; and said second operation is an operation in which, if saidresult of said first operation is “fail”, said data stored in saidregister is changed to increase said initial voltage by a predeterminedvoltage.
 41. A method of testing a semiconductor device, saidsemiconductor device having an internal circuit in which an output istrimmed in 2^(N) different schemes by a register capable of holdingN-bit data (where N denotes a positive integer), said method of testinga semiconductor device comprising: judging in a first test said outputof said internal circuit while said N-bit data is placed in a firststate, to determine most significant bit data of said N-bit data;judging, in a kth test (k=2, 3, . . . N), while data from said mostsignificant bit to a (k−1)th bit is maintained to a value determined ina first to (k−1)th test, said output of said internal circuit with saidremaining bit being-placed in a predetermined value to determine a kthbit data; and setting data reflecting characteristics of eachsemiconductor device to said register by said N tests.
 42. The method oftesting a semiconductor device, according to claim 41, wherein saidregister stores a bit that indicates whether or not a test fordetermining data stored in said register is carried out.
 43. A method oftesting a semiconductor device, said semiconductor device comprising amemory cell array in which programmable and erasable nonvolatile memorycells are arranged in column and row directions of a matrix; a senseamplifier; and a bit line extending in said column direction, configuredto transmit data of said memory cell array to said sense amplifier,wherein, said method of testing a semiconductor device, comprisesdetermining whether or not an open-circuit, short-circuit or leak ispresented in said bit line and sense amplifier to detect a defectivecolumn of said memory cell array, without carrying out writing anderasing operation for said memory cells.
 44. The method of testing asemiconductor device, according to claim 43, wherein, data is read outby said sense amplifier while said memory cells connected to said bitline are all placed in an non-selected state and said bit line isconnected to a predetermined potential, and an open-circuit state ofsaid bit line is detected according to a readout data by said senseamplifier.
 45. A method of detecting and replacing a defective column ina semiconductor device, said semiconductor device comprising a memorycell array having a column region and a row region in which memory cellsare arranged in column and row directions of a matrix; a redundancycolumn region having M redundancy columns for replacement with adefective column in said memory cell array; M registers configured tostore column addresses to be replaced with said redundancy columns, eachof said M registers including a latch placed to a first or second signalstate according to whether or not a corresponding redundancy column canbe used; a sense amplifier; a counter that selects said M registerssequentially; and a judgment circuit that makes a judgment on whether ornot data of a selected column outputted from said sense amplifiercoincides with a predetermined expected value and outputs a “pass” or“fail” signal according to a result of said judgment, wherein, saidmethod of detecting and replacing a defective column in a semiconductordevice comprising: setting a column address and said counter to astarting address, when a defective column in said memory cell array isto be detected; making, if an output of said judgment circuit is “pass”,an increment of said column address, and, if said output of saidjudgment circuit is “fail” and said latch of said register selected bysaid counter is placed in said first signal state, storing said columnaddress in said register and thereafter making an increment of saidcolumn address and said counter after; making an increment of saidcounter until said counter has reached a register whose latch is placedin said first signal state, if said output of said judgment circuit is“fail” and said latch of said register selected by said counter isplaced in said second signal state, thereafter, storing said columnaddress in said register, and thereafter, making an increment of saidcolumn address and said counter; and carrying out said above operationsuntil said counter has reached an end column address.
 46. The method ofdetecting and replacing a defective column in a semiconductor device,according to claim 45, wherein a first operation configured to detect adefect in said redundancy column region is carried out prior to a secondoperation configured to detect a defective column in said memory cellarray, and said latch of said register is placed in said second signalstate, which register corresponds to a redundancy column in which adefect has been detected, and a column address is set in said registernot to select said column region of said memory cell array.